Difference between revisions of "Processor Performance"
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− | = | + | ==Overview== |
+ | ===CraigNDave=== | ||
<youtube>https://www.youtube.com/watch?v=SQy_wg9oZl0&index=123&list=PLCiOXwirraUDUYF_qDYcZV8Hce8dsE_Ho</youtube> | <youtube>https://www.youtube.com/watch?v=SQy_wg9oZl0&index=123&list=PLCiOXwirraUDUYF_qDYcZV8Hce8dsE_Ho</youtube> | ||
https://www.youtube.com/watch?v=SQy_wg9oZl0&index=123&list=PLCiOXwirraUDUYF_qDYcZV8Hce8dsE_Ho (MDR is same as MBR) | https://www.youtube.com/watch?v=SQy_wg9oZl0&index=123&list=PLCiOXwirraUDUYF_qDYcZV8Hce8dsE_Ho (MDR is same as MBR) | ||
+ | |||
+ | ===Computer Science Tutor=== | ||
+ | <youtube>eS1rEJZKr4U</youtube> | ||
+ | |||
+ | https://www.youtube.com/watch?v=eS1rEJZKr4U&list=PL04uZ7242_M6O_6ITD6ncf7EonVHyBeCm&index=20 | ||
+ | |||
+ | ===TRC Video=== | ||
+ | <youtube>https://www.youtube.com/watch?v=kYxO3T2aqhI</youtube> | ||
+ | |||
+ | https://www.youtube.com/watch?v=kYxO3T2aqhI | ||
==Cache Memory== | ==Cache Memory== | ||
− | Cache Memory is a very fast but expensive type of memory which is normally located on the processor itself. It will be used to store instructions which follow current one. This will mean less need to use slower memory, and data can be pre-fetched before it is used by the processor. The greater cache means more fast speed memory that allows programs to execute faster. | + | Cache Memory is a very fast but expensive type of memory which is normally located on the processor itself. It will be used to store instructions which follow the current one. It will also be used to store the instructions for a loop, so that each iteration doesn't require the instructions to be fetched. |
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+ | This will mean less need to use slower memory, and data can be pre-fetched before it is used by the processor. The greater cache means more fast speed memory that allows programs to execute faster. | ||
==Increase clock speed== | ==Increase clock speed== | ||
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==Increase word length== | ==Increase word length== | ||
− | When the word length is exceeded, the speed is greatly reduced (this can be as a result of an error in calculations or input). By increasing the word length you are less likely to exceed it. Increasing word length would also allow for more instructions and addresses, this will speed up the processor because a complex set of instructions could be replaced by a new instruction. | + | When the word length is exceeded, the speed is greatly reduced (this can be as a result of an error in calculations or input). By increasing the word length you are less likely to exceed it. |
+ | |||
+ | Increasing word length would also allow for more instructions and addresses, this will speed up the processor because a complex set of instructions could be replaced by a new instruction. | ||
==Increase Data Bus width== | ==Increase Data Bus width== | ||
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==Increase Address Bus width== | ==Increase Address Bus width== | ||
− | More memory addresses can be used and accessed, this will therefore allow more system memory. This will speed up the computer because more | + | More memory addresses can be used and accessed, this will therefore allow more system memory. This will speed up the computer because more instructions or data can be pre-loaded ready for use. |
==Multi-core== | ==Multi-core== |
Latest revision as of 08:19, 23 August 2023
Contents
Overview
CraigNDave
https://www.youtube.com/watch?v=SQy_wg9oZl0&index=123&list=PLCiOXwirraUDUYF_qDYcZV8Hce8dsE_Ho (MDR is same as MBR)
Computer Science Tutor
https://www.youtube.com/watch?v=eS1rEJZKr4U&list=PL04uZ7242_M6O_6ITD6ncf7EonVHyBeCm&index=20
TRC Video
https://www.youtube.com/watch?v=kYxO3T2aqhI
Cache Memory
Cache Memory is a very fast but expensive type of memory which is normally located on the processor itself. It will be used to store instructions which follow the current one. It will also be used to store the instructions for a loop, so that each iteration doesn't require the instructions to be fetched.
This will mean less need to use slower memory, and data can be pre-fetched before it is used by the processor. The greater cache means more fast speed memory that allows programs to execute faster.
Increase clock speed
More cycles per second, therefore less seconds until a task is finished. Every task will be executed in a shorter time.
Increase word length
When the word length is exceeded, the speed is greatly reduced (this can be as a result of an error in calculations or input). By increasing the word length you are less likely to exceed it.
Increasing word length would also allow for more instructions and addresses, this will speed up the processor because a complex set of instructions could be replaced by a new instruction.
Increase Data Bus width
More data is passed at once which results in more data been processed for the task per cycle. Therefore data can be loaded in a shorter time.
Increase Address Bus width
More memory addresses can be used and accessed, this will therefore allow more system memory. This will speed up the computer because more instructions or data can be pre-loaded ready for use.
Multi-core
Processors are traditionally made up of a single core (ie one processor). However this approach greatly increased the heat generated. The clock speed of the fastest processors reached above 5gz. The faster the clock speed the more heat was generated.
To combat this they started to create processors with 2 separate cores (ie 2 processors on the same silicon). These were called dual-core processors and the combined clock speed should give similar performance, for example 2 1gz processors are similar to 1 2gz processor. but the dual core processor will run at a lower temperature.This has continued so we now have Quad(4), Hexa(6), Octo(8) and even 16 and 32 cores on many server processors.
The speed doesn't always work in reality because software needs to be written in a way that supports multiple processors. Often some software will use just a single core and therefore not using the full potential of the processor. The speed is also affected by processor scheduling, the goal is to keep all of the processors busy however instructions are often dependent on the previous instructions. This will cause the core to stop until the dependent instruction is carried out.