Difference between revisions of "Fetch Decode Execute Cycle"
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Revision as of 11:38, 23 May 2017
Contents
Fetch Decode Execute Cycle
Fetch Transfer Notation
[PC] -> MAR
[Memory] -> MBR
[PC] + 1 -> PC
[MBR] -> CIR
Explanation
The address of the next instruction to be executed is copied from the Program Counter to the Memory Address Register.
The instruction at that address is then copied to the Memory Buffer Register.
Simultaneously, the contents of the Program Counter are incremented by 1.
The contents of the Memory Buffer Register are copied to the Current Instruction Register.
