Difference between revisions of "Fetch Decode Execute Cycle"
(Created page with " =Fetch Decode Execute Cycle= ==Fetch Transfer Notation== [PC] -> MAR [Memory] -> MBR [PC] + 1 -> PC [MBR] -> CIR ===Explanation=== The address of the next instruction...") |
(→Decode Transfer Notation) |
||
| Line 23: | Line 23: | ||
==Decode Transfer Notation== | ==Decode Transfer Notation== | ||
| − | + | [CIRop-code] → CU | |
===Explanation=== | ===Explanation=== | ||
| + | The op code from the CIR is passed to the Control Unit | ||
==Execute Transfer Notation (LOAD)== | ==Execute Transfer Notation (LOAD)== | ||
Revision as of 08:15, 16 June 2017
Contents
Fetch Decode Execute Cycle
Fetch Transfer Notation
[PC] -> MAR
[Memory] -> MBR
[PC] + 1 -> PC
[MBR] -> CIR
Explanation
The address of the next instruction to be executed is copied from the Program Counter to the Memory Address Register.
The instruction at that address is then copied to the Memory Buffer Register.
Simultaneously, the contents of the Program Counter are incremented by 1.
The contents of the Memory Buffer Register are copied to the Current Instruction Register.
Decode Transfer Notation
[CIRop-code] → CU
Explanation
The op code from the CIR is passed to the Control Unit
